-- ************************************************* -- = == -- * | | /* -- ** ------- * | |/ * -- * *====| |====| | | | -- ** ------- * | |\ * -- * | | \* -- ELEKTRONIK = == -- ENTWICKLER -- AACHEN -- -- Adresse: -- F.Juergen Gensicke, Dipl.-Ing. (FH) -- Kirberichshofer Weg 31, D-52066 Aachen -- -- Tel.: +49 / 241 / 47580488 -- Mobil: +49 / 173 / 2931531 -- E-Mail: info@ee-ac.de -- ************************************************* -- Entwickelt fuer: -- -- Firmennamen -- -- Adresse: -- Firma -- Ansprechpartner -- Strasse, D-PLZ Ort -- -- Tel.: +49 / Vorwahl / Anschluss -- Mobil: +49 / Vorwahl / Anschluss -- E-Mail: E-Mail-Adresse -- ************************************************* -- Datei: speicherram.vhd -- Autor: F.Juergen Gensicke -- Datum: 07.04.2011 -- ************************************************* -- Beschreibung : -- -- Diese VHDL-Datei erzeugt ein 8-Bit Register. -- -- Revisionen: -- ============================= -- Aenderung am DATUM Version X: -- Autor: F.Juergen Gensicke -- Was?: -- Text mit Aenderungsbeschreibung -- Design Goal: Timing -- Strategie: Performance with IO Packaging -- ************************************************* -- Libraries: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library altera; use altera.altera_primitives_components.all; -- ************************************************* entity speicherram is Port ( CLK : in std_logic; RST : in std_logic; Adressen : in std_logic_vector(7 downto 0); Daten : inout std_logic_vector(7 downto 0); nRD : in std_logic; nWR : in std_logic; nCS : in std_logic ); end speicherram; architecture arc_speicherram of speicherram is signal DatenIn, DatenOut : std_logic_vector(7 downto 0); signal WREN, T : std_logic; component ram8x8 port ( aclr : IN STD_LOGIC ; address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); clock : IN STD_LOGIC ; data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); end component; BEGIN -- ########################################### -- Single-ended Bi-directional Buffer -- ########################################### IOBUF_Bit0 : ALT_IOBUF generic map ( IO_STANDARD => "Differential 1.2-V HSTL Class I", CURRENT_STRENGTH_NEW => "4mA", ENABLE_BUS_HOLD => "none", WEAK_PULL_UP_RESISTOR => "off", LOCATION => "IOBANK_3C" ) port map ( i => DatenOut(0), oe => T, o => DatenIn(0), io => Daten(0) ); IOBUF_Bit1 : ALT_IOBUF generic map ( IO_STANDARD => "Differential 1.2-V HSTL Class I", CURRENT_STRENGTH_NEW => "4mA", ENABLE_BUS_HOLD => "none", WEAK_PULL_UP_RESISTOR => "off", LOCATION => "IOBANK_3C" ) port map ( i => DatenOut(1), oe => T, o => DatenIn(1), io => Daten(1) ); IOBUF_Bit2 : ALT_IOBUF generic map ( IO_STANDARD => "Differential 1.2-V HSTL Class I", CURRENT_STRENGTH_NEW => "4mA", ENABLE_BUS_HOLD => "none", WEAK_PULL_UP_RESISTOR => "off", LOCATION => "IOBANK_3C" ) port map ( i => DatenOut(2), oe => T, o => DatenIn(2), io => Daten(2) ); IOBUF_Bit3 : ALT_IOBUF generic map ( IO_STANDARD => "Differential 1.2-V HSTL Class I", CURRENT_STRENGTH_NEW => "4mA", ENABLE_BUS_HOLD => "none", WEAK_PULL_UP_RESISTOR => "off", LOCATION => "IOBANK_3C" ) port map ( i => DatenOut(3), oe => T, o => DatenIn(3), io => Daten(3) ); IOBUF_Bit4 : ALT_IOBUF generic map ( IO_STANDARD => "Differential 1.2-V HSTL Class I", CURRENT_STRENGTH_NEW => "4mA", ENABLE_BUS_HOLD => "none", WEAK_PULL_UP_RESISTOR => "off", LOCATION => "IOBANK_3C" ) port map ( i => DatenOut(4), oe => T, o => DatenIn(4), io => Daten(4) ); IOBUF_Bit5 : ALT_IOBUF generic map ( IO_STANDARD => "Differential 1.2-V HSTL Class I", CURRENT_STRENGTH_NEW => "4mA", ENABLE_BUS_HOLD => "none", WEAK_PULL_UP_RESISTOR => "off", LOCATION => "IOBANK_3C" ) port map ( i => DatenOut(5), oe => T, o => DatenIn(5), io => Daten(5) ); IOBUF_Bit6 : ALT_IOBUF generic map ( IO_STANDARD => "Differential 1.2-V HSTL Class I", CURRENT_STRENGTH_NEW => "4mA", ENABLE_BUS_HOLD => "none", WEAK_PULL_UP_RESISTOR => "off", LOCATION => "IOBANK_3C" ) port map ( i => DatenOut(6), oe => T, o => DatenIn(6), io => Daten(6) ); IOBUF_Bit7 : ALT_IOBUF generic map ( IO_STANDARD => "Differential 1.2-V HSTL Class I", CURRENT_STRENGTH_NEW => "4mA", ENABLE_BUS_HOLD => "none", WEAK_PULL_UP_RESISTOR => "off", LOCATION => "IOBANK_3C" ) port map ( i => DatenOut(7), oe => T, o => DatenIn(7), io => Daten(7) ); RAMBLOCK: ram8x8 PORT MAP ( aclr => RST, address => Adressen, clock => CLK, data => DatenIn, wren => WREN, q => DatenOut ); -- ########################################### -- Concurrent Statements -- ########################################### T <= '1' when (nRD = '0' and nCS = '0') else '0'; -- ########################################### -- RAM-Speicherzugriff -- ########################################### process (CLK, RST) begin if (RST='1') then WREN <= '0'; elsif (CLK'event and CLK='1') then -- CLK rising edge WREN <= NOT(nWR) and nRD and NOT(nCS); end if; end process; end arc_speicherram;